The present invention relates to formation of back end of the line (BEOL) interconnect structures in integrated circuits, and more specifically, to improved methods for BEOL processes with improved spacer height and defect reduction.
Back-end-of-line (BEOL) interconnect structures are used to electrically connect the device structures fabricated on the substrate during front-end-of-line (FEOL) processing. BEOL processes can involve complex patterning schemes, including multiple patterning schemes. Such patterning schemes can result in formation of spacers with differing and potentially detrimentally tall heights, which can adversely affect product reliability.